1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, it relates to a technique effective for forming an input protection circuit of a MOS structure device.
2. Description of the Background Art
A MOS structure semiconductor element having a gate oxide film represented by a power MOSFET (metal oxide semiconductor field-effect transistor) or an IGBT (insulated gate bipolar transistor) requires an input protection circuit for protecting the semiconductor element against a surge current or static electricity, as well known in the art. When a surge current or static electricity flows into a gate electrode of the MOS structure semiconductor element, remarkable deterioration is readily caused on the electrostatic characteristic of a gate insulator film of the MOS structure semiconductor element. In general, therefore, a bidirectional Zener diode is provided between a gate electrode and a source electrode of a power MOSFET as the aforementioned input protection circuit, as shown in an equivalent circuit of FIG. 39. Such a countermeasure is disclosed in the description of paragraph [0002] and FIG. 4 in Japanese Patent Application Laid-Open Gazette No. 7-321305 (1995), for example.
FIG. 40 is a top plan view showing the layout of a semiconductor device having a plurality of MOS structure semiconductor elements and an input protection circuit therefor, which is also employed in later description of an embodiment 1 of the present invention and modifications thereof.
FIG. 41 is a top plan view schematically showing an input protection Zener diode forming region hatched in FIG. 40 among regions formed on the upper surface of a base layer of the aforementioned semiconductor device in an enlarged manner. The input protection Zener diode forming region is hereinafter referred to as a first region, and a region formed with a MOS transistor structure having a gate electrode and a main electrode is referred to as a second region. The definition of these regions also applies to later description of the embodiment 1, an embodiment 2 and modifications thereof. As shown in FIG. 41, a Zener diode is formed by alternately forming p-type semiconductor layers and n-type semiconductor layers in the form of rings.
FIG. 42 is a longitudinal sectional view of the Zener diode taken along the line I-II in FIG. 41. FIG. 43 is a longitudinal sectional view of an n-type diffusion region (n-type semiconductor layer) of the Zener diode taken along the line III-IV in FIG. 41.
As shown in FIGS. 41 to 43, an n-type second semiconductor substrate 2 containing low-concentration n-type impurities is formed on an n-type first semiconductor substrate 1 containing high-concentration n-type impurities by epitaxy. The substrates 1 and 2 form an n-type base semiconductor layer. Further, an insulator film 3 of an oxide film or the like is formed on the base semiconductor layer (1, 2). An input protection circuit is formed on a base layer defined by the base semiconductor layer (1, 2) and the insulator film 3 by the following manufacturing method: A polysilicon layer 4 is formed on the base layer, for successively forming an n-type semiconductor layer 4b1 having a square cross-sectional or planar shape, a p-type semiconductor layer 4a1 having a ring cross-sectional shape, a ring-shaped n-type semiconductor layer 4b2, a ring-shaped p-type semiconductor layer 4a2 and a ring-shaped n-type semiconductor layer 4b3 in the polysilicon layer 4 to enclose a gate pad formed after formation of the Zener diode. Thus, a bidirectional Zener diode having a plurality of p-n junction surfaces is formed as the input protection circuit.
Thereafter the Zener diode is overcoated with an interlayer isolation film 5, and contact holes 6a and 6b are provided on portions located immediately above the innermost n-type semiconductor layer 4b1 and the outermost n-type semiconductor layer 4b3 of the ring-shaped Zener diode respectively for bringing the n-type semiconductor layers 4b1 and 4b3 into ohmic contact with a gate electrode layer 7a and a source electrode layer 7b through the contact holes 6a and 6b respectively. Thereafter another interlayer isolation film (not shown) is formed on the gate electrode layer 7a and the source electrode layer 7b and an opening is formed in part of this interlayer isolation film located on the gate electrode layer 7a, thereby partially exposing the gate electrode layer 7a. The exposed part of the gate electrode 7a defines the aforementioned gate pad.
A reverse withstand voltage of the aforementioned Zener diode is set to a desired value by adjusting the number of the p-type and n-type semiconductor layers forming the Zener diode or adjusting the impurity concentrations of the p-type and n-type semiconductor layers.
For example, Japanese Patent Application Laid-Open Gazettes Nos. 7-321305 (1995), 8-288525 (1996) and 9-97901 (1997) disclose a Zener diode having a structure corresponding to such a longitudinal sectional structure.
The input protection circuit having the aforementioned structure protects the gate insulator film of the MOS structure semiconductor element against a surge current or static electricity. However, the effect of the conventional input protection circuit for protecting the gate insulator film cannot still be said sufficient since the value of parasitic resistance of the diode in the conventional input protection circuit is unignorably large due to the specification of the apparatus. Consider that surge takes place, for example. Also when feeding a surge current from the gate electrode toward the source electrode through the aforementioned diode at this time, a voltage determined by the product of the parasitic resistance value of the diode and the surge current is applied across the diode, to cause remarkable deterioration in characteristics of the gate oxide film as the case may be. In other words, it follows that characteristic deterioration of the gate oxide film readily takes place as the parasitic resistance value of the diode is increased regardless of the surge current flowing to the diode, to remarkably damage the function of the diode serving as the input protection circuit.
Such a problem is caused also when static electricity is generated in the MOS structure semiconductor element.
It is well known that the parasitic resistance value of the diode is inversely proportionate to the peripheral length (corresponding to the length of the diode or each semiconductor region shown in FIG. 41 in a peripheral direction PD) of the diode and the thickness of the polysilicon layer in each p-n junction surface and proportionate to the width (corresponding to the length in a direction perpendicular to the peripheral direction PD) of each semiconductor region in the diode.
Therefore, the peripheral length of the diode or the thickness of the polysilicon layer may be increased or the width of each semiconductor region may be reduced thereby reducing the parasitic resistance value of the diode and improving the function of the diode serving as the input protection circuit.
When simply increasing the peripheral length of the diode, however, a new problem arises to enlarge the chip size. When the area occupied by the diode itself, inclusive of the area occupied by the gate pad, is increased, the peripheral length of the diode is also increased in response thereto, while activation regions of the MOS transistors are narrowed to result in such a problem that the number of the MOS transistors cannot be increased to a necessary level. Occurrence of such a problem is serious particularly in a semiconductor device originally having a small chip size.
While increase of the thickness of the polysilicon films employed for the diode brings reduction of manufacturability, while such a structural restriction results from increase of the thickness of the polysilicon layers that each semiconductor region must be elongated along the width in order to cope with increase of transverse diffusion of p-type and n-type impurities in the diode.
When narrowing the widths of the p-type and n-type semiconductor regions in the diode, further, it follows that voltage resistance is deteriorated due to reach-through, and hence this countermeasure cannot be preferable either.
According to a first aspect of the present invention, a semiconductor device comprises a base layer and a diode arranged on an upper surface of the base layer, while the diode comprises a plurality of semiconductor regions extending in a first direction respectively and successively forming p-n junctions in a second direction perpendicular to the first direction, the conductivity type of a first semiconductor region located on the side of a first end in the second direction among the plurality of semiconductor regions of the diode is equal to the conductivity type of a second semiconductor region located on the side of a second end opposed to the first end, and the interface between the base layer and the diode in the upper surface of the base layer comprises a plurality of groove portions having a depth in a third direction perpendicular to the first direction and the second direction, extending in the second direction and successively arranged in the first direction.
According to a second aspect of the present invention, at least one of the plurality of semiconductor regions of the diode comprises an irregular portion having an irregular shape defined by the plurality of groove portions of the interface.
According to a third aspect of the present invention, at least one of the plurality of semiconductor regions of the diode comprises an upper surface having a flat portion opposed to a bottom surface of each of the plurality of groove portions of the interface in the third direction.
According to a fourth aspect of the present invention, the base layer comprises a base semiconductor layer of a prescribed conductivity type and an insulator film arranged on an upper surface of the base semiconductor layer, and the insulator film comprises an upper surface opposed to an interface between the base semiconductor layer and the insulator film in the third direction and corresponding to the interface between the base layer and the diode.
According to a fifth aspect of the present invention, each of the plurality of groove portions is defined as a first groove portion, and the interface between the base semiconductor layer and the insulator film comprises a plurality of second groove portions each opposed to the first groove portion.
According to a sixth aspect of the present invention, a first thickness of the insulator film arranged on a portion of the interface between the base semiconductor layer and the insulator film held between two adjacent second groove portions among the plurality of second groove portions in the third direction is larger than a second thickness of the insulator film arranged on a bottom surface of each of the plurality of second groove portions in the third direction.
According to the sixth aspect, the parasitic resistance of the diode can be further reduced, and the protective function for the gate insulator film can be further improved.
According to a seventh aspect of the present invention, the prescribed conductivity type of the base semiconductor layer is a first conductivity type, and the base layer further comprises a plurality of semiconductor well regions of a second conductivity type extending from a portion located under a bottom surface of each of the plurality of groove portions in the interface between the base semiconductor layer and the insulator film into the base semiconductor layer.
According to the seventh aspect, the voltage resistance of the semiconductor device can be improved.
According to an eighth aspect of the present invention, the semiconductor device further comprises a MOS transistor structure, comprising a gate electrode and a main electrode, arranged on a second region in the upper surface of the base layer when defining a portion of the upper surface of the base layer provided with the diode as a first region, while the first semiconductor region is electrically connected with the gate electrode and the second semiconductor region is electrically connected with the main electrode.
According to a ninth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of forming an insulator film on a semiconductor substrate, forming an irregular portion on the insulator film, forming a semiconductor film on the insulator film comprising the irregular potion and alternately forming a p-type semiconductor region and an n-type semiconductor region in the semiconductor film in prescribed order thereby forming a diode of a multilayer structure.
According to the first, second, third, fourth, eighth and ninth aspects, the diode can have a peripheral length not only in the transverse direction but also in the vertical direction although the area occupied by the diode as viewed from above is identical to that of the prior art, whereby the peripheral length of the diode is increased, the area of a p-n junction surface is responsively increased, the sectional area of a path for a surge current is increased, and parasitic resistance is remarkably reduced. Therefore, a clamping effect of the diode is increased to improve surge resistance, and the function of protecting the gate insulator film is improved.
According to a tenth aspect of the present invention, a method of manufacturing a semiconductor device comprises steps of forming an irregular portion on a semiconductor substrate, forming an insulator film on a surface of the semiconductor substrate comprising the irregular portion, forming a semiconductor film on the insulator film and alternately forming a p-type semiconductor region and an n-type semiconductor region in the semiconductor film in prescribed order thereby forming a diode of a multilayer structure.
According to the fifth and tenth aspects, the parasitic resistance of the diode can be further reduced, and the protective function for the gate insulator film can be further improved.
An object of the present invention is to provide a semiconductor device capable of reducing the area of a Zener diode for an input protection circuit and improving an input protection function.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.